Typically, in an information processing apparatus including a sequential circuit, latch circuits (latch devices) synchronized by clock signals for retaining internal data are present in large numbers. In such latch circuits, with an aim to confirm whether the circuits are correctly manufactured or to confirm the internal data or to set arbitrary data inside the circuits, a popular practice is to configure in advance a scan chain in the circuits (for example, see Japanese Laid-open Patent Publication No. 2002-139545). The latch circuits with such a scanning function are referred to as scanning-capable latch circuits.
In FIG. 5 is illustrated a configuration of a conventional scanning-capable latch circuit 100. During normal system operations, data input from a data input terminal D illustrated in FIG. 5 is synchronized to clock signals CLK and XCLK and stored in a master circuit that functions as the main latch circuit. At the same time, the data is output from an output terminal MS.
During a scanning operation, clock signals ACK and XACK for scanning output switch to the ON state while the clock signals CLK and XCLK remain in the OFF state. Then, the data stored in the master circuit is copied into a slave circuit that functions as a slave latch circuit. At the same time, the data is output from a scanning result output terminal SO.
Moreover, when the clock signals ACK and XACK switch to the OFF state and clock signals BCK and XBCK for scanning input switch to the ON state, the data copied into the slave circuit is retained as it is and the data input from a scanning signal input terminal SI is loaded in the master circuit.
In FIG. 6 is illustrated a time chart of the conventional scanning operation. As illustrated in FIG. 6, the data in the master circuit is copied into and latched at the slave circuit by the clock signals ACK and XACK, while the scanning input is latched at the master circuit by the clock signals BCK and XBCK. This processing is equivalent to a single cycle.
In FIG. 7 is illustrated a scan chain that is configured by serially connecting m number of the scanning-capable latch circuit 100. Herein, scanning output SO from each scanning-capable latch circuit becomes scanning input SI for the subsequent scanning-capable latch circuit.
When the abovementioned single cycle is performed in the scan chain, the data gets shifted by a single bit. Thus, when switching ON/OFF of the clock signals ACK and BCK is repeated for the number of times equal to the number of latch circuits (with reference to FIG. 7, repeated for m number of times), it is possible to retrieve the internal data from the scanning result output terminal SO as well as it is possible to set data in an internal latch from the scanning signal input terminal SI.
However, in the conventional scanning-capable latch circuit, the entire slave circuit as well as a scanning-clock-signal input component inside the master circuit illustrated in FIG. 5 are configured solely for the purpose of scanning. Besides, from the perspective of system operations, the master circuit except the scanning-clock-signal input component would suffice. Hence, providing a scanning circuit on a latch causes a significant increase in the circuit area.